(a) Field of the Invention
The present invention relates to a method for manufacturing a semiconductor device and, more particularly, to a method for manufacturing a semiconductor device having a doped silicon film.
(b) Description of the Related Art
A DRAM (dynamic random access memory) device generally includes a memory cell array area wherein a plurality of memory cells are arranged in a two-dimensional array, and a peripheral circuit area wherein a peripheral circuit for driving the memory cells is disposed. The memory cells each include a MOSFET formed on a surface region of a silicon substrate, and a capacitor connected to the MOSFET for storing therein electric charge or data. In general, the electric charge stored in the capacitor gradually reduces due to the junction leakage current as the time elapses. Thus, the DRAM device operates refreshing the data by restoring the electric charge in the capacitor after reading the stored electric charge within the time interval specified for read out of the electric charge.
In the DRAM device installed in an electronic equipment, especially in a portable electronic equipment, it is ever desired to reduce the power dissipation to extend the battery life for the electronic equipment. For this purpose, it is preferable to reduce the power source voltage of the electronic equipment, and to improve the data retention capability of the memory cells for increasing the time interval between refreshing operations which consume a larger amount of power.
A literature presented on “Symposium on VLSI Technology”, pp 11-12, 2003 describes a RCAT device or recessed-channel MOSFET for improving the data retention capability of the memory cells including the MOSFET. The recessed-channel MOSFET is a specific MOSFET including a gate electrode made of silicon, which is received in a recess formed in a surface region of the silicon substrate.
In the recessed-channel MOSFET, a U-character channel is formed along the surface of the recess, whereby a larger channel length is obtained even in a semiconductor device manufactured with a smaller design rule. The recessed-channel MOSFET achieves a specific threshold voltage for a channel having an impurity concentration lower than that for the channel of a planar MOSFET. This allows the recessed-channel MOSFET to have a lower electric field across the p-n junction, thereby reducing the junction leakage current to improve the data retention capability of the memory cells.
In a process for manufacturing the recessed-channel MOSFET, the recess is formed in the surface region of the silicon substrate, followed by deposition of a silicon electrode film on the silicon substrate including the internal of the recess via the gate insulation film. The silicon electrode film is doped with a dopant or impurities by ion implantation and then subjected to patterning thereof to form gate electrodes. A heat treatment is then conducted to diffuse the dopant within the gate electrodes for activation of the dopant, thereby obtaining the gate electrodes having a higher electric conductivity.
On the other hand, it is desired to allow MOSFETs formed in the peripheral circuit area to have a smaller channel length for achieving a higher operational speed. Thus, planar cell array transistors (planar MOSFETs) are preferably used as the MOSFETs in the peripheral circuit area.
The inventor analyzed the process for manufacturing the recessed-channel MOSFETs in the memory cell array area and planar MOSFETs in the peripheral circuit area. In order for improving the through-put of the process for the DRAM device, it is preferable to conduct ion-implantation of the silicon electrode film in the recessed-channel MOSFETs and is the silicon electrode film in the planar MOSFETs in the peripheral circuit area in a single step, if both the silicon electrode films includes specific conductivity-type impurities, i.e, p-type or n-type dopant.
However, the single implantation step has a problem in that the acceleration energy of the ion-implantation of the silicon electrode film in the peripheral circuit area should be adapted to a smaller thickness of the silicon electrode film therein, although the silicon electrode film of the recessed-channel MOSFETs have a larger thickness. The smaller acceleration energy adapted to a smaller thickness of the silicon electrode film cannot allow the impurities to be well diffused within the depth of the bottom surface of the silicon electrode film in the memory cell array area. This situation is schematically shown in FIG. 3, wherein the character “P” represents phosphor (P) atoms (ions) and that the number of characters “P” indicates the impurity concentration at respective depths of the silicon electrode film in the recessed-channel MOSFETs. FIG. 3 reveals that a portion of a larger depth has a lower impurity concentration. FIG. 4 shows the impurity profile in the structure shown in FIG. 3 plotted on the vertical plane taken along IV-IV line in FIG. 3.
The lower impurity concentration near the bottom of the silicon electrode film 16 causes depletion of the gate electrodes during operation of the recessed-channel MOSFETs, thereby reducing the ON-current of the MOSFETs and degrades the operational speed of the DRAM device.
For suppressing the insufficient impurity concentration near the bottom of the recess 14 in FIG. 3, it may be considered to perform in-situ doping during deposition of the silicon electrode film 16. In this case, if the silicon electrode film includes n-type impurities such as “P” due to the in-situ doping, it is necessary to dope the n-type silicon electrode film deposited in the PMOS region, which has an n-type conductivity, with a p-type dopant such as “B” to have a p-type conductivity opposite to that of the original PMOS region, as shown in FIG. 5.
The inversion of the conductivity type should be performed to implant the silicon electrode film with the p-type impurity atoms in number which is well larger than the number of n-type impurity atoms introduced during the in-situ doping, as shown in FIG. 5. In FIG. 5, “P” denotes phosphorous ions and “B” denotes boron ions. The larger number of p-type impurity atoms, “B”, introduced in the ion-implantation may cause the problem of diffusion of the p-type impurity atoms toward the silicon substrate 11, as depicted by “B” placed in the channel region in FIG. 5. This causes a change or variation of threshold voltage of the MOSFETs.